Sandboxes
Real tools running real code in isolation — not a syntax highlighter pretending to compile. Write, run, and inspect the results.
Write real code, run it instantly in an isolated sandbox, and see it work. No installs, no licenses, no lab machine — just a browser. Explore free demos, then go deep with graded courses.
Free to start · An account is required to run code
The product
Every engineering domain on Zenzei is built the same way: a real execution sandbox at the centre, free demos to draw you in, and graded courses to take you further. One account covers all of them.
Real tools running real code in isolation — not a syntax highlighter pretending to compile. Write, run, and inspect the results.
Ready-to-run designs with nothing to prove. Open one, hit run, break it, and read the waveform. No grading, no pass or fail.
Structured exercises graded automatically against a real testbench. You write the code; the simulator decides whether it works.
Domains
The platform underneath — accounts, content, security, entitlements — is shared. Opening a new domain means adding a sandbox, not rebuilding the product.
SystemVerilog and UVM on our own simulator — assertions, functional coverage, and waveform dumps included. Demos and graded lessons are live now.
A full in-browser workspace — file tree, editor, and an integrated waveform viewer — for when a single-file sandbox is not enough.
The same demos-and-courses shape, pointed at models instead of silicon. Plus an AI assistant that understands the code you are writing.
Why Zenzei
Zenzei runs on Zenith, a SystemVerilog simulator we develop ourselves. Every engineer who uses the platform makes it better — which is why the sandbox stays free.
Hardware today, AI next. One account, one set of progress, one place to learn the engineering disciplines that are converging anyway.
Compiles, elaborates, simulates. You get the log, the assertion results, the coverage, and the waveform — the same artifacts you would get from a commercial flow.
No licence server, no toolchain, no VM. Verification tooling has been locked behind six-figure licences for decades — this is the way in.
How it works
Open a demo or a lesson and edit SystemVerilog in a real code editor, right in the browser.
Your code is queued to our simulator, compiled, and executed in an isolated sandbox.
Read the log, check assertions and coverage, and download the waveform to see what actually happened.
Inside
A sample of what is in the sandbox today. Create an account to open any of them.
ALU Explorer
beginnerA classic 8-bit ALU with six operations — run it and watch the result table print, then trace the buses in the waveform.
Open demo →Parameterized FIFO
intermediateA synchronous FIFO with random push/pop backpressure — the demo to open the waveform on: flags, pointers, and data flow all visible.
Open demo →AXI-Lite Handshake Bug Hunt
intermediateSVA assertions guard the valid/ready handshake — and catch a deliberate bvalid-drop bug. Watch protocol checking in action.
Open demo →UVM Hello World
advancedA complete minimal UVM environment — sequence, driver, monitor, scoreboard, and a covergroup — in one readable file.
Open demo →Pricing
Everything on Zenzei is free during early access. When paid tiers arrive, individual and community use stays free — we decided that early so there is never a bait-and-switch.
$0 / forever
Later
Not available yet. Individual use stays free regardless.
An account takes a few seconds and costs nothing. The simulator is waiting on the other side.
Get started free