Sandboxes
Real tools running real code in isolation — not a syntax highlighter pretending to compile. Write, run, and inspect the results.
Open beta — public demo planned for late December
Learn hardware and AI engineering by building it.
Write real code, run it instantly in an isolated sandbox, and see it work. No installs, no licenses, no lab machine — just a browser. Zenzei is in open beta: create a free account and help us test it.
Free beta account · Limited availability — the simulator may not be online 24/7
SystemVerilogUVMAssertions / SVAFunctional coverageWaveformsSelf-checking testbenches
The product
A live sandbox, wrapped in things worth learning.
Every engineering domain on Zenzei is built the same way: a real execution sandbox at the centre, demos to explore, and courses to take you further. One account covers all of them.
Demos
Ready-to-run designs with nothing to prove. Open one, hit run, break it, and read the waveform. No grading, no pass or fail.
Courses
Structured, step-by-step exercises built around real designs and testbenches. You write the code and run it yourself.
Domains
Chip verification today. More engineering next.
The platform underneath — accounts, content, security, entitlements — is shared. Opening a new domain means adding a sandbox, not rebuilding the product.
RTL / Design Verification
Open betaSystemVerilog and UVM on our own simulator — assertions, functional coverage, and waveform dumps included. Demos and lessons are open for beta testing.
Interactive IDE
OnlineA full in-browser workspace — file tree, editor, and an integrated waveform viewer — for when a single-file sandbox is not enough.
AI engineering
PlannedThe same demos-and-courses shape, pointed at models instead of silicon. Plus an AI assistant that understands the code you are writing.
Why Zenzei
We build the tools, not just the lessons.
Our own simulator
Zenzei runs on a SystemVerilog simulator we develop ourselves. Every run during the beta helps us find what to fix and harden it.
One platform, many domains
Hardware today, AI next. One account, one set of progress, one place to learn the engineering disciplines that are converging anyway.
Real code, really executed
Compiles, elaborates, simulates. You get the log, the assertion results, the coverage, and the waveform — the same artifacts you would get from a commercial flow.
Nothing to install
No licence server, no toolchain, no VM. Verification tooling has been locked behind six-figure licences for decades — this is the way in.
How it works
Three steps, no setup.
- 01
Write
Open a demo or a lesson and edit SystemVerilog in a real code editor, right in the browser.
- 02
Run
Your code is queued to our simulator, compiled, and executed in an isolated sandbox.
- 03
Explore
Read the log, check assertions and coverage, and download the waveform to see what actually happened.
Inside
Designs waiting to be run.
A sample of what is in the sandbox today. Create an account to open any of them.
ALU Explorer
TraineeA classic 8-bit ALU with six operations — run it and watch the result table print, then trace the buses in the waveform.
Open demo →Parameterized FIFO
RegularA synchronous FIFO with random push/pop backpressure — the demo to open the waveform on: flags, pointers, and data flow all visible.
Open demo →AXI-Lite Handshake Bug Hunt
RegularSVA assertions guard the valid/ready handshake — and catch a deliberate bvalid-drop bug. Watch protocol checking in action.
Open demo →UVM Hello World
SeniorA complete minimal UVM environment — sequence, driver, monitor, scoreboard, and a covergroup — in one readable file.
Open demo →Pricing
Free during the open beta.
Zenzei is a beta: it is still being built, and the simulator is not online all the time. Create a free account to test the platform. A public demo is planned for late December — what stays free after that has not been decided yet, and we will say so before anything changes.
Beta access
Open beta$0 during the beta
- Platform access for beta testing
- Demos and lessons, run and explore
- Logs and waveform downloads
- Limited availability while we build
Pro
PlannedLater
To be defined.
Stop reading about verification. Go run something.
Join the open beta. An account takes a few seconds and is free, and every run you make helps us build a better simulator.
Join the open beta